RTL Engineer

The Mission for the RTL Engineer role

Your mission is to create magic on silicon for a brand-new chip company. Design silicon that will be the talk of the town, laying the foundation for our growth into a global semiconductor powerhouse.
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Outcomes

In the first three to six months, you will create, verify, and optimise RTL code for our second chip, which will go into production in early 2025. Over the next few years, you will work on extracting the most from silicon for our upcoming chips.
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Pay

As per industry standards for the hardware industry, plus ESOP.
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What will your week look like?

You will be a part of the RTL engineering team and will work on designing, implementing, and verifying digital logic, as well as simulation, emulation, and verification of Vision SoC, our second chip. You might also work on optimising and verifying the RTL code for our first chip, Secure IoT before it goes for mass volume production in mid-2025. Occasionally, you will also have to create and maintain design documentation.

In this role, you will be closely coordinating with three teams

• The verification team, who write test benches to make sure designs meet functional requirements
• The architects and design leads who define microarchitecture and implement functional blocks
• The physical design team, who ensure closure on timing, power and area constraints.

You will work in the IIT Madras Research Park in Chennai. You will have to invest time and energy every week to improve your technical knowledge of the field, any new developments that occur and your understanding of the tools we use. To that end, many of our employees are pursuing an MS in IIT Madras, and the same option might be open for you.

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How to Apply

Fill the form with your details and the answers to the pre-interview test (submit a public URL for your pre interview questions in PDF Format)

1/ Assume the time scale is in seconds for the verilog code given below. What will be the delay after which each of the registers a, b, c, d, e, f will be set to 1?

 module register_set () ;
 reg a , b , c , d , e , f ;

 initial begin
 a = #10 1’ b1 ;
 b = #20 1’ b1 ;
 c = #40 1’ b1 ;
 end

 initial begin
 d <= #10 1’ b1 ;
 e <= #20 1’ b1 ;
 f <= #40 1’ b1 ;
 end

 endmodule


2/ Design a digital circuit which implements y = 2x + c from the template given below. Note - Try without using behavioral constructs.

module multiplier_adder ( input [3:0] x , input c , output [4:0] y);
 /*
 your design goes here
 */
 endmodule


3/ Write a verilog test bench to implement a clock generator which generates 125 MHz clock signal.

4/ What is CDC reconvergence issue?

• Technical knowledge of the field is important. The candidate should have an undergraduate degree in electrical engineering, computer science or any relevant field.
• You need to have a strong understanding of digital design principles, including timing, power, and area optimization.
• Between 3-5 years of experience in RTL design and implementation on silicon or FPGA.
• Since you will interact with multiple teams, communication skills are very critical - both written and verbal.
• Proficiency in Verilog, UVM and System Verilog.
• Experience with industry-standard EDA tools like Synopsys, Cadence and/or Mentor.
• We’re on a crazy mission to compete with global giants like TI, NXP, etc. So, the candidate must have the inbuilt desire and motivation to take on a tough challenge.